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cy7c135 cy7c135a cy7c1342 4k x 8 dual-port static ram and 4k x 8 dual-port sram with semaphores cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06046 rev. *f revised november 10, 2010 features true dual-ported memory cells, which allow simultaneous reads of the same memory location 4k x 8 organization 0.65 micron cmos for optimum speed and power high speed access: 15 ns low operating power: i cc = 160 ma (max) fully asynchronous operation automatic power down semaphores included on the 7c1342 to permit software handshaking between ports available in 52-pin plastic leaded chip carrier (plcc) pb-free packages available functional description the cy7c135/135a [1] and cy7c1342 are high speed cmos 4k x 8 dual-port static rams. the cy7c1342 includes semaphores that provide a means to allocate portions of the dual-port ram or any shared resource. two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). the cy7c135/135a is suit ed for those systems t hat do not require on-chip arbitration or are intolerant of wait states. therefore, the user must be aware that simultaneous access to a location is possible. semaphores are offered on the cy7c1342 to assist in arbitrating between ports. the semaphore logic is comprised of eight shared latches. only o ne side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip enable (ce ) pin or sem pin (cy7c1342 only). the cy7c135/135a and cy7c1342 are available in 52-pin plcc. r/w l ce l oe l a 11l a 0l a 0r a 11r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r semaphore arbitration (7c1342 only) control i/o control i/o memory array address decoder address decoder (7c1342 only) sem l sem r (7c1342 only) logic block diagram note 1. cy7c135 and cy7c135a are functionally identical [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 2 of 15 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 pin definitions .................................................................. 3 maximum ratings.............................................................. 4 operating range ............................................................... 4 electrical characteristics.................................................. 4 electrical characteristics ................................................. 5 capacitance ....................................................................... 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 7 architecture .................................................................... 10 functional description ................................................... 10 write operation ......................................................... 10 read operation ......................................................... 10 semaphore operation ............ .............. .............. ....... 10 typical dc and ac characteristics .............................. 11 ordering information ...................................................... 12 4k x8 dual-port sram .............................................. 12 ordering code definition .... ....................................... 12 package diagram ............................................................. 13 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 3 of 15 pin configurations figure 1. pin diagram - cy7c135/135a (top view ) figure 2. pin diagram - cy7c1342 (top view) selection guide parameter 7c135-15 7c1342-15 7c135-20 7c1342-20 7c135/135a-25 7c1342-25 7c135-35 7c1342-35 7c135-55 7c1342-55 unit maximum access time 15 20 25 35 55 ns maximum operating current commercial 220 190 180 160 160 ma maximum standby current for i sb1 commercial 60 50 40 30 30 ma 1 v cc 7c135/135a 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe n/c a r/w ce r/w 0l l l l ce r r a 10l a 10r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l n/c a 11r a 11l a 11r 1 v cc 7c1342 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe sem a r/w ce r/w sem 0l l l l l ce r r r a 10l a 10r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l a 11l pin definitions left port right port description a 0l?11l a 0r?11r address lines ce l ce r chip enable oe l oe r output enable r/w l r/w r read/write enable sem l (cy7c1342 only) sem r (cy7c1342 only) semaphore enable. when asserted low, allows access to eight semaphores. the three least significant bits of the address lines determin es which semaphore to write or read. the i/o 0 pin is used when writing to a semaphore. semaphor es are requested by writing a 0 into the respective location. [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 4 of 15 maximum ratings [2] exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 ? c to+150 ? c ambient temperature with power applied ............................................ ?55 ? c to+125 ? c supply voltage to ground potential (pin 48 to pin 24).................... ...................... ?0.5 v to+7.0 v dc voltage applied to outputs in high z state .............................................. ?0.5 v to+7.0 v dc input voltage [3] ........................................?3.0 v to +7.0 v static discharge voltage........................................... > 2001 v (per mil-std-883, method 3015) latch up current...................................................... > 200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 5 v 10% industrial ?40 ? c to +85 ? c5 v 10% electrical characteristics over the operating range parameter description test conditions 7c135-15 7c1342-15 7c135-20 7c1342-20 7c135-25 7c135a-25 7c1342-25 unit min max min max min max v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? 2.4 ? 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma ? 0.4 ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 v i ix input load current gnd ? v i ? v cc ?10 +10 ?10 +10 ?10 +10 ? a i oz output leakage current outputs disabled, gnd ? v o ? v cc ?10 +10 ?10 +10 ?10 +10 ? a i cc operating current v cc = max., i out = 0 ma com?l ? 220 ? 190 ? 180 ma ind. ? ? ? ? ? 190 i sb1 standby current (both ports ttl levels) ce l and ce r ?? v ih , f = f max [4] com?l ? 60 ? 50 ? 40 ma ind. ? ? ? ? ? 50 i sb2 standby current (one port ttl level) ce l and ce r ? v ih , f = f max [4] com?l ? 130 ? 120 ? 110 ma ind. ? ? ? ? 120 i sb3 standby current (both ports cmos levels) both ports ce and ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, f = 0 [4] com?l ? 15 ? 15 ? 15 ma ind. ? ? ? ? ? 30 i sb4 standby current (one port cmos level) one port ce l or ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, active port outputs, f = f max [4] com?l ? 125 115 100 ma ind. ? ? ? ? ? 115 notes 2. the voltage on any input or i/o pin cannot exceed the power pin during power up. 3. pulse width < 20 ns. 4. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3. [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 5 of 15 electrical characteristics over the operating range (continued) parameter description test conditions 7c135-35 7c1342-35 7c135-55 7c1342-55 unit min max min max v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min., i ol = 4.0 ma ? 0.4 ? 0.4 v v ih 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 v i ix input load current gnd ? v i ? v cc ?10 +10 ?10 +10 ? a i oz output leakage current outputs disabled, gnd ? v o ? v cc ?10 +10 ?10 +10 ? a i cc operating current v cc = max., i out = 0 ma com?l ? 160 ? 160 ma v cc = max., i out = 0 ma ind. ? 180 ? 180 i sb1 standby current (both ports ttl levels) ce l and ce r ? v ih , f = f max [5] com?l ? 30 ? 30 ma ind. ? 40 ? 40 i sb2 standby current (one port ttl level) ce l and ce r ? v ih , f = f max [5] com?l ? 100 ? 100 ma ind. ?110?110 i sb3 standby current (both ports cmos levels) both ports ce and ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, f = 0 [5] com?l ? 15 ? 15 ma ind. ? 30 ? 30 i sb4 standby current (one port cmos level) one port ce l or ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, active port outputs, f = f max [5] com?l ? 90 ? 90 ma ind. ? 100 ? 100 capacitance [6] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 10 pf figure 3. ac test loads and waveforms notes 5. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or contro l lines change. this applies only to inputs at cmos level standby i sb3. 6. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd 90% 90% 10% ? 3ns ? 3 ns 10% all input pulses (a) normal load (load 1) r1 = 893 ? 5v output r1 = 347 ? c = 30 pf r th = 250 ? v th = 1.4v output c = 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 3) v x output r th = 250 ? c = 5 pf [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 6 of 15 switching characteristics over the operating range [7] parameter description 7c135-15 7c1342-15 7c135-20 7c1342-20 7c135-25 7c135a-25 7c1342-25 7c135-35 7c1342-35 7c135-55 7c1342-55 unit min max min max min max min max min max read cycle t rc read cycle time 15?20?25?35?55? ns t aa address to data valid ?15?20?25?35?55ns t oha output hold from address change3?3?3?3?3?ns t ace ce low to data valid ?15?20?25?35?55ns t doe oe low to data valid ?10?13?15?20?25ns t lzoe [8,9,10] oe low to low z 3?3?3?3?3?ns t hzoe [8,9,10] oe high to high z ?10?13?15?20?25ns t lzce [8,9,10] ce low to low z 3?3?3?3?3?ns t hzce [8,9,10] ce high to high z ?10?13?15?20?25ns t pu [10] ce low to power-up 0?0?0?0?0?ns t pd [10] ce high to power-down ?15?20?25?35?55ns write cycle t wc write cycle time 15 ? 20 ? 25 ? 35 ? 55 ? ns t sce ce low to write end 12?15?20?30?50? ns t aw address setup to write end 12?15?20?30?50? ns t ha address hold from write end 2?2?2?2?2?ns t sa address setup to write start 0?0?0?0?0?ns t pwe write pulse width 12?15?20?25?50? ns t sd data setup to write end 10?13?15?15?25? ns t hd data hold from write end 0?0?0?0?0?ns t hzwe [9,10] r/w low to high z ?10?13?15?20?25ns t lzwe [9,10] r/w high to low z 3?3?3?3?3?ns t wdd [11] write pulse to data delay ? 30 ? 40 ? 50 ? 60 ? 70 ns t ddd [11] write data valid to read data valid ? 25 ? 30 ? 30 ? 35 ? 40 ns semaphore timing [12] t sop sem flag update pulse (oe or sem ) 10?10?10?15?15? ns t swrd sem flag write to read time 5?5?5?5?5?ns t sps sem flag contention window 5?5?5?5?5?ns notes 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30 pf load capacitance. 8. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 9. test conditions used are load 3. 10. this parameter is guaranteed but not tested. 11. for information on port-to-port delay through ram cells from writing port to reading port, refer to figure 6 . 12. semaphore timing applies only to cy7c1342. [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 7 of 15 switching waveforms t rc t aa t oha data valid previous data valid data out address either port address access figure 4. read cycle no. 1 [13,14] t ace t lzoe t doe t hzoe t hzce data valid data out sem or ce oe t lzce t pu i cc i sb t pd either port ce /oe access figure 5. read cycle no. 2 [13,15] [12] valid t ddd t wdd match match r/w r data inr data outl t wc address r t pwe valid t sd t hd address l figure 6. read timi ng with port-to-port [16] notes 13. r/w is high for read cycle. 14. device is continuously selected, ce = v il and oe = v il . 15. address valid prior to or coincident with ce transition low. 16. ce l = ce r =low; r/w l = high [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 8 of 15 switching waveforms (continued) t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe t lzoe sem or ce r/w address oe data out data in figure 7. write cycle no. 1: oe three-states data i/os (either port) [17, 18, 19] [20] t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance sem or ce r/w address data out data in t lzwe data valid figure 8. write cycle no. 2: r/w three-states data i/os (either port) [18, 21] [20] notes 17. the internal write time of the memory is defined by the overlap of ce or sem low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and ho ld timing should be referenced to the rising edge of the signal that terminates the write. 18. r/w must be high during all address transactions. 19. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during a r/w controlled write cycle (as in this example) , this requirement does not apply and the write pulse can be as s hort as the specified t pwe . 20. semaphore timing applies only to cy7c1342. 21. data i/o pins enter high impedance when oe is held low during write. [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 9 of 15 switching waveforms (continued) t sop t aa sem r/w oe i/o 0 valid address valid address t hd data in valid data out valid t oha a 0 ?a 2 t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle figure 9. semaphore read after write timing, either side (cy7c1342 only) [22] match t sps match r/w l sem l r/w r sem r figure 10. timing diagram of semaphore contention (cy7c1342 only) [23, 24, 25] a 0l ?a 2l a 0r ?a 2r notes 22. ce = high for the duration of the above timing (both write and read cycle). 23. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 24. semaphores are reset (availabl e to both ports) at cycle start. 25. if t sps is violated, it is guaranteed that only one side gains access to the semaphore. [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 10 of 15 architecture the cy7c135/135a consists of an array of 4k words of 8 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). two semaphore control pins exist for the cy7c1342 (sem l/r ). functional description write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. because there is no on-chip arbitration, the user must be sure that a specific location is not accessed simultaneously by both ports or erroneous data could result. a write operation is controlled by either the oe pin (see figure 7 ) or the r/w pin (see figure 8 ). data can be written t hzoe after the oe is deasserted or t hzwe after the falling edge of r/w . required inputs for write operations are summarized in ta b l e 1 . if a location is being written to by one port and the opposite port attempts to read the same location, a port-to-port flowthrough delay is met before the data is valid on the output. data is valid on the port wishing to read the location t ddd after the data is presented on the writing port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe are asserted. if the user of the cy7c1342 wishes to access a semaphore, the sem pin must be asserted instead of the ce pin. required inputs for read operations are summarized in ta b l e 1 . semaphore operation the cy7c1342 provides eight semaphore latches, which are separate from the dual port memory locations. semaphores are used to reserve resources which are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes cont rol over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip enable for the semaphore latches. ce must remain high during sem low. a 0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a 0 is written to the left port of an unused semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing a zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore. table 2 shows sample semaphore operations. when reading a semaphore, all eight data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both po rts request a semaphore control by writing a 0 to a semaphore within t sps of each other, it is guaranteed that only one side gains access to the semaphore. initialization of the semaphore is not automatic and must be reset during initialization program du ring power up. all semaphores on both sides should have a one written into them at initialization from both sides to assure that they are free when needed. table 1. non-contending read/write inputs outputs operation ce r/w oe sem i/o 0 ? i/o 7 h x x h high z power-down h h l l data out read semaphore x x h x high z i/o lines disabled h l x l data in write to semaphore l h l h data out read l l x h data in write l x x l illegal condition table 2. semaphore operation example function i/o 0-7 left i/o 0-7 right status no action 1 1 semaphore free left port writes semaphore 0 1 left port obtains semaphore right port writes 0 to semaphore 0 1 right side is denied access left port writes 1 to semaphore 1 0 right port is granted access to semaphore left port writes 0 to semaphore 1 0 no change. left port is denied access right port writes 1 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore address right port writes 0 to semaphore 1 0 right port obtains semaphore right port writes 1 to semaphore 1 1 no port accessing semaphore left port writes 0 to semaphore 0 1 left port obtains semaphore left port writes 1 to semaphore 1 1 no port accessing semaphore [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 11 of 15 typical dc and ac characteristics 100 80 70 60 0.0 1.0 2.0 3.0 5.0 50 90 4.0 4.0 4.5 5.0 5.5 6.0 140 120 100 80 60 40 0 1.0 2.0 3.0 5.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature ( ? c) output voltage (v) output source current vs. output voltage 0.0 normalized i cc , i sb 0 i cc 1.2 1.1 1.0 0.9 ?55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature ( ? c) 1.05 1.00 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage output sink current (ma) output voltage (v) output sink current vs. output voltage 0.8 0.95 1.25 1.0 0.75 10 50 normalized i cc 0.50 normalized i cc vs. cycle time cycle frequency (mhz) 1.0 0.75 0.25 0 1.0 2.0 3.0 5.0 normalized t pc 20.0 10.0 5.0 0 200 400 600 800 delta t aa (ns) 0 15.0 0.0 supply voltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 0.50 20 30 i sb normalized i cc , i sb 25 1.10 40 1.0 0.6 0.4 1.2 0.2 20 t a = 25 ? c 4.0 1.4 ?55 25 125 1.2 1.0 0.8 0.6 0.6 v cc = 5.0v i cc 0.2 0.4 i sb3 0.8 v in = 5.0v v cc = 5.0v t a = 25 ? c v cc = 5.0v v cc = 5.0v t a = 25 ? c t a = 25 ? c v cc = 4.5v v cc = 5.0v t a = 25 ? c v in = 5.0v [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 12 of 15 ordering code definition ordering information 4k x8 dual-port sram speed (ns) ordering code package name package type operating range 15 CY7C135-15JXC j69 52-pin pb-free plastic leaded chip carrier commercial 25 cy7c135?25jxi j69 52-pin pb-free plastic leaded chip carrier industrial cy 7 c xxx x company id: cy = cypress marketing code: 7 = sram technology : cmos density operating range c = commercial i = industrial xx speed: 15 ns / 25 ns xx x: pb-free package: (j69) 52 pin plastic leaded chip carrier [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 13 of 15 acronyms document conventions units of measure package diagram figure 11. 52-pin pb-free plastic leaded chip carrier j69 51-85004 *b acronym description cmos complementary metal oxide semiconductor tqfp thin quad plastic flatpack i/o input/output sram static random access memory plcc plastic leaded chip carrier symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes ? ohms mv milli volts mhz mega hertz pf pico farad wwatts c degree celcius [+] feedback
cy7c135 cy7c135a cy7c1342 document #: 38-06046 rev. *f page 14 of 15 document history page document title: cy7c135, cy7c135a, cy7c1342 4k x 8 dual-p ort static ram and 4k x 8 dual-port sram with semaphores document number: 38-06038 rev. ecn no. orig. of change submission date description of change ** 110181 szv 10/21/01 change from spec number: 38-00541 to 38-06038 *a 122288 rbi 12/27/02 power up requirements added to maximum ratings information *b 236763 ydt see ecn removed cross information from features section *c 393413 yim see ecn added pb-free logo added pb-free parts to ordering information: CY7C135-15JXC, cy7c135-25jxc *d 2623540 vkn/pyrs 12/17/08 added cy7c135a parts removed cy7c1342 from the ordering information table *e 2897217 rame 03/22/2010 updated ordering information updated package diagram *f 3081925 admu 11/10/2010 added ordering code definition details added acronyms and units of measure table. updated all the footnotes updated the datasheet as per new template [+] feedback
document #: 38-06046 rev. *f revised november 10, 2010 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c135 cy7c135a cy7c1342 ? cypress semiconductor corporation, 2010. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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